1. Field of the Invention
The present invention relates to the field of manufacturing of semiconductor devices and micro electro-mechanical systems (MEMS), and more particularly to the formation of spacers.
2. Discussion of Related Art
For many years spacers have been employed in the manufacture of semiconductor and MEMS devices. Generally, a spacer is a material ultimately retained only on the sidewalls of non-planar structures. The formation of a spacer typically proceeds by depositing a film over a non-planar structure and anisotropically etching the film by an amount sufficient to at least the as-deposited thickness of the film. The anisotropic character of the etch process leaves a spacer only where deposition of the film on the sidewall of the non-planar structure increases the effective thickness of the film. Therefore, the thickness of the film deposited on the sidewall determines the final spacer thickness after the bulk of the film has been etched away.
One reason the conventional spacer process has found wide application in industry is because of its “self-aligned” nature. The formation of the spacer itself requires only a blanket deposition and an unpatterned anisotropic etch to consistently form a spacer of a controlled lateral thickness (i.e. width) adjacent to another feature from the sidewall of the non-planar structure. Unfortunately, as devices have become more advanced, the self-aligned nature of a spacer begins to have significant disadvantages. For example, more advanced devices have more severe topography and the need to prevent a spacer from forming on a particular sidewall of a device may be in conflict with the need to form a spacer on another sidewall of the same device.
Conventional multi-gate transistor 100 in FIG. 1A, serves to illustrate this point further. A non-planar semiconductor body 115, having sidewall 107 with sidewall height H1, and top surface 108, is formed adjacent to isolation 110 over substrate 102. Top surface 108 and sidewall 107 are apportioned into a non-planar source/drain regions 116 and a channel region. The channel region is that portion of non-planar semiconductor body 115 covered by a gate stack with a sidewall height H2 and comprised of gate insulator 112 and gate electrode 113. In this transistor design, the device can be gated by the gate stack through sidewall 107 as well as the top surface 108 of the device. Because the channel is gated by multiple gate electrode-semiconductor interfaces, the transistor having a non-planar channel is frequently called a multi-gate device.
As further shown in FIG. 1A, spacer 119 is formed to offset or “space” non-planar source/drain regions 116 from the channel region covered by the gate stack. The self-aligned nature of the conventional spacer formation process dictates that spacer 118 is formed adjacent to sidewall 107 by the same process that forms spacer 119. While spacer 119 is desirable, spacer 118 may be undesirable because, for example, spacer 118 limits access to non-planar semiconductor body 115 in non-planar source/drain regions 116. Thus, undesirable spacer 118 leaves only the area of the top surface of non-planar source/drain regions 116 having length L and width W accessible to subsequent processing. Therefore, the non-selective nature of the conventional spacer shown in FIG. 1A can be problematic.
FIG. 1B represents a cross-sectional view of the multi-gate transistor of FIG. 1A taken along the A-A′ reference line. Here again, spacer 118, undesired, is adjacent to non-planar semiconductor body 115 extending over isolation 110 on substrate 102. Spacer 119, desired, is adjacent to gate stack 114. Also visible in FIG. 1B is etch damage to semiconductor surface 125 spanning the length L of the top surface of non-planar source/drain regions 116. Damage to semiconductor surface 125 is a result of exposing semiconductor surface 125 to a plasma-based anisotropic etch during a conventional spacer formation process.